3D revolution in GaN transistors
Cambridge Electronics, Inc. (CEI) has pioneered a new way of making GaN devices [1]: 3DGaN technology. Unlike the conventional 2D structure used in previous generation GaN devices, a third dimension utilized by our 3DGaN technology opens up new possibilities that were not accessible before, such as reducing the transistor leakage current, making normally-off transistors [1] and significantly improving the linearity for 5G applications [2, 3].
Recognized by the IEEE Electron Devices Society's George E. Smith Award, our team continues to innovate and push the boundaries of GaN technology.
Recognized by the IEEE Electron Devices Society's George E. Smith Award, our team continues to innovate and push the boundaries of GaN technology.
The first 8" GaN FinFET processed in Si foundry
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Conventional GaN transistors are fabricated in 4-inch and 6-inch wafer fabs using expensive manufacturing process. Thanks to our patented etch-stop technology [4], we have developed 8-inch process technology using standard Si-foundries. By leveraging the existing Si foundry and taking the advantage of Moor's law, we are bringing our advanced 3DGaN technology to high volume production and continuing performance improvement with technology scaling.
Recently, CEI is selected as one of the nine awardees of the ARPA-E SCALEUP (Seeding Critical Advances for Leading Energy technologies with Untapped Potential) program to bring this game-changing technology to high volume production for datacenter and 5G applications. |
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Superior reliability from physics based design
Over the past 13 years, our team has been at the cutting-edge of GaN research, revealing ground breaking physics governing breakdown mechanisms [5], dynamic on-resistance [6], dielectric-GaN interface traps [7], and degradation mechanisms [8]. Building on this strong foundation, we take a physics-focused approach to design devices with superior performance and reliability and solve the key instability issue such as the dynamic Ron/current collapse of GaN transistors.
Normally-off technology
Normally-off transistors have the advantage of blocking high voltages without the need of an extra negative bias to the gate terminal. As a result, they greatly simplify circuit designs.
The most common approaches for making normally-off GaN transistors are using either 1) cascode where a Si FET is used in series connection with a normally-on GaN transistor or 2) p-GaN gate. However, both of these approaches have drawbacks such as compromised switching performance, increased the cost, or poor gate robustness. Our team is developing a more advanced approach that is to make true normally-off insulating-gate GaN transistors which overcomes the drawbacks of both the cascode and pGaN-gate normally-off GaN FETs and works more like Si MOSFET.
While the normally-off insulating-gate GaN technology is the most desirable technology, it is also the most challenging to develop. With many years' research, our team has achieved several significant milestones: record channel mobility at the MISFET interface [4, 7]; high uniformity; and the industry best threshold voltage (Vth) stability.
The most common approaches for making normally-off GaN transistors are using either 1) cascode where a Si FET is used in series connection with a normally-on GaN transistor or 2) p-GaN gate. However, both of these approaches have drawbacks such as compromised switching performance, increased the cost, or poor gate robustness. Our team is developing a more advanced approach that is to make true normally-off insulating-gate GaN transistors which overcomes the drawbacks of both the cascode and pGaN-gate normally-off GaN FETs and works more like Si MOSFET.
While the normally-off insulating-gate GaN technology is the most desirable technology, it is also the most challenging to develop. With many years' research, our team has achieved several significant milestones: record channel mobility at the MISFET interface [4, 7]; high uniformity; and the industry best threshold voltage (Vth) stability.
Publications:
[1] B. Lu, E. Matioli, and T. Palacios, "Tri-gate normally-off GaN Power MISFET," IEEE Electron Device Letters, 33 (3), pp. 360-362, Mar. 2012.
[2] D.S. Lee, et. al. and T. Palacios, "nanowire channel inAlGaN/GaN HEMTs with high linearity of gm and fT," IEEE Electron Device Letters, 34 (8), pp.969-971, Aug. 2013.
[3] S. Joglekar, et. al. and T. Palacios, "Large signal linearity enhancement of AlGaN/GaN high electron mobility transistors by device-level Vt engineering for transconductance compensation," in IEEE International Electron Devices Meeting (IEDM) Dig., Dec. 2017, pp. 25.3.1-4.
[4] B. Lu, M. Sun and T. Palacios, "An etch-stop barrier structure for GaN high electron mobility transistors," IEEE Electron Device Letters, 34 (3), pp. 990-992, Mar. 2013.
[5] B. Lu, E. L. Piner and T. Palacios, “Breakdown Mechanism in AlGaN/GaN HEMTs on Si Substrate”, in IEEE 68th Device Research Conf. (DRC) Dig., Jun. 2010, pp.193-194.
[6] B. Lu, T. Palacios, D. Risbud, S. Bahl and D. I. Anderson, “Extraction of dynamic on-resistance in GaN transistors under soft-and hard-switching conditions,” in IEEE Compound Semiconductor Integrated Circuit Symp. (CSICS), Oct. 2011, pp. 1-4.
[7] B. Lu, M. Sun and T. Palacios, “Interface Analysis and Modeling of Normally-Off GaN MISFETs with an Etch-Stop-Barrier Structure,” presented at 10th International Conference on Nitride Semiconductors (ICNS-10), Washington DC, Aug. 2013.
[8] B. Lu, F. Gao, C.V. Thompson, T. Palacios, “Role of Electrochemical Reactions in the Degradation Mechanisms of AlGaN/GaN HEMTs,” invited talk at CS Mantech, Denver, May 2014.
[1] B. Lu, E. Matioli, and T. Palacios, "Tri-gate normally-off GaN Power MISFET," IEEE Electron Device Letters, 33 (3), pp. 360-362, Mar. 2012.
[2] D.S. Lee, et. al. and T. Palacios, "nanowire channel inAlGaN/GaN HEMTs with high linearity of gm and fT," IEEE Electron Device Letters, 34 (8), pp.969-971, Aug. 2013.
[3] S. Joglekar, et. al. and T. Palacios, "Large signal linearity enhancement of AlGaN/GaN high electron mobility transistors by device-level Vt engineering for transconductance compensation," in IEEE International Electron Devices Meeting (IEDM) Dig., Dec. 2017, pp. 25.3.1-4.
[4] B. Lu, M. Sun and T. Palacios, "An etch-stop barrier structure for GaN high electron mobility transistors," IEEE Electron Device Letters, 34 (3), pp. 990-992, Mar. 2013.
[5] B. Lu, E. L. Piner and T. Palacios, “Breakdown Mechanism in AlGaN/GaN HEMTs on Si Substrate”, in IEEE 68th Device Research Conf. (DRC) Dig., Jun. 2010, pp.193-194.
[6] B. Lu, T. Palacios, D. Risbud, S. Bahl and D. I. Anderson, “Extraction of dynamic on-resistance in GaN transistors under soft-and hard-switching conditions,” in IEEE Compound Semiconductor Integrated Circuit Symp. (CSICS), Oct. 2011, pp. 1-4.
[7] B. Lu, M. Sun and T. Palacios, “Interface Analysis and Modeling of Normally-Off GaN MISFETs with an Etch-Stop-Barrier Structure,” presented at 10th International Conference on Nitride Semiconductors (ICNS-10), Washington DC, Aug. 2013.
[8] B. Lu, F. Gao, C.V. Thompson, T. Palacios, “Role of Electrochemical Reactions in the Degradation Mechanisms of AlGaN/GaN HEMTs,” invited talk at CS Mantech, Denver, May 2014.